This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-297672, filed Sep. 28, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor device and more specifically to a MIS field effect transistor (MISFET) of three-dimensional structure.
2. Description of the Related Art
There have been proposals for double-gate fully depleted-SOI MOSFETs which are one type of MISFETs of three-dimensional structure (D. Hisamoto et al. :IEDM 1998 P.1032, X. Huang et al. :IEDM 1999 P.67, Jpn. Pat. Appln. KOKAI Publication No. 2-263473, and Japanese Examined Patent Application No. 2768719). The double-gate fully depleted-SOI MOSFET comprises a SOI (Silicon on Insulator) substrate, a single-crystal silicon strip, and a gate electrode. The single-crystal silicon strip has been made by etching the uppermost layer of the SOI substrate, i.e., a single-crystal silicon layer. The gate electrode lies above the the silicon strip and extends across the silicon strip. The upper surface region and side regions of the strip serve as the channel.
The above MOSFETs provide high current drivability, are more economical of space in the direction of gate width than conventional MOSFETs, and have the short-channel effect controlled. They are therefore promising for devices used in future LSIs.
FIGS. 1A, 1B and 1C show the pattern layout and sections of the MOSFETS. On a semiconductor substrate 101 is formed an insulating layer 102, which is in turn formed on top with a silicon fin layer 103. A source 105 and a drain 106 are formed over the silicon fin layer 103 on opposite sides thereof with an insulating film 104 interposed therebetween.
An insulating film 108 is formed on the source 105 and the drain 106 in order to insulate the source and the drain from a gate electrode 107 to be formed. Also, an insulating film 109 is formed on the sidewall of the groove between the source 105 and the drain 106 in order to insulate them from the gate electrode 107. The gate electrode 107 is formed in the groove.
The implementation of this device involves the use of an expensive SOI substrate, which will increase the manufacturing cost of LSIs that are expected to be mass-produced. In addition, the device reliability may be subject to the quality of the SOI substrate.
A device adapted to perform the same operation as the device of SOI structure as illustrated in FIGS. 1A, 1B and 1C can be implemented using a normal bulk substrate. The device based on a bulk substrate has a substrate projection which forms a device region and is implemented by selectively oxidizing the bottom of the device region.
FIG. 2 is a perspective view of a conventional device using a bulk substrate and FIG. 3 is a cross-sectional view of the device. As shown in FIGS. 2 and 3, an insulating film 112 is formed on a semiconductor substrate 111. A source 113 and a drain 114 are formed on the insulating film 112. A gate electrode 116 is formed over a semiconductor layer 110 between the source 113 and the drain 114 with a gate insulating film 115 interposed therebetween.
With the device shown in FIGS. 2 and 3, however, a decrease in the size of the device region may make it difficult to control the thickness of the oxide film and may cause deformation due to thermal oxidation at high temperatures to affect the device performance
With respect to the SOI structure in the aforementioned two devices, it is known that, since the thermal conductivity of the insulating file existing under the silicon layer is lower than that of crystal silicon, self-heating occurs due to Joule heat generated by drain current to cause a degradation in the drain current. Therefore, the devices shown in FIGS. 1A to 1C and FIGS. 2 and 3 cannot necessarily display the performance fully for application to LSIs.
In devices of the SOI structure, holes generated by impact ionization in the channel have their escape cut off and are trapped in the lower portion of the channel, causing the so-called substrate floating effect. This phenomenon is remarkably observed particularly in n-channel field effect transistors. For this reason, there is fear that the substrate floating effect might affect the operation of high-speed switching devices in particular.
An example of a MISFET that is allowed to have a three-dimensional structure through the use of a bulk substrate is one illustrated in U.S. Pat. No. 5,844,278. With this MISFET, the bulk substrate is processed to have a projection shape and the substrate projection shape is made to have such a gate electrode structure as in the aforementioned prior art.
FIGS. 4 and 5 are sectional views of the MISFET in steps of manufacture thereof.
As shown in FIG. 4, a protruding region 121A is formed on a semiconductor substrate 121. A gate insulating film 122 is formed on the protruding region 121A. An insulating film 123 is formed on opposite sides of the protruding region 121A. A mask material 124 is formed on the insulating film 123.
In the structure of FIG. 4, the device is subjected to an ion implantation operation to prevent the occurrence of punch-through in deep portions of source and drain diffusion layers. This ion implantation allows a heavily doped region 125 to be formed at the bottom of the protruding region 121A.
Furthermore, as shown in FIG. 5, shallow source and drain regions 126 are formed in the top surface and the side surface of the protruding region 121A, thereby allowing each of the top surface and the side surface to operate as an almost independent MISFET.
The MISFET shown in FIGS. 4 and 5 is not a device of the SOI structure; for the protruding region 121A and the underlying semiconductor substrate 121 are joined together. Thus, the MISFET has advantages that heat due to the Joule effect and the substrate floating effect are decreased.
However, trying to reduce the gate length (for example, 0.1 xcexcm or less) and operate the device as a completely depleted one makes difficult the process of manufacturing the structure shown in FIGS. 4 and 5. Thus, the demand has increased for developing a structure having a novel structure adapted for the generation of devices in which the gate length is 0.1 xcexcm or less.
According to an aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor projection having a semiconductor layer of a first conductivity type and side surfaces and a top surface, the semiconductor projection being formed on a semiconductor substrate of the first conductivity type; a gate electrode formed above at least the side surfaces of the semiconductor projection with a gate insulating film interposed therebetween; source and drain regions of a second conductivity type formed in the side surfaces of the semiconductor projection so that they are located on opposite sides of the gate electrode; first and second device isolation insulating films formed over the semiconductor substrate on opposite sides of the semiconductor projection; a first impurity region of the first conductivity type formed in a portion of the semiconductor substrate below the first device isolation insulating film; and a second impurity region of the first conductivity type formed in a portion of the semiconductor substrate below the second device isolation insulating film, the second impurity region being in contact with the first impurity region in a portion of the semiconductor substrate below the semiconductor projection.